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HY5DU28422ET HY5DU28822ET HY5DU281622ET
128Mb DDR SDRAM
HY5DU28422ET HY5DU28822ET HY5DU281622ET
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 /Apr. 2006
HY5DU28422ET HY5DU28822ET HY5DU281622ET
Revision History
Revision No. 0.1 0.2 0.3 Define Preliminary Specification Insert CL3 in Speed Grade(-J) Editorial Changes 1) Changed Document Title from 128M to 128Mb 2) Changed Parameter name from Ambient Temperature to Operating Temperature in ABSOLUTE MAXIMUM RATINGS 3) Updated High, Low Current Level of Output Driver Strength in DC OPERATING CONDITIONS 4) Corrected 6th note and Added 7th note in DC OPERATING CONDITIONS 5) Editorial Changes State Diagram modified History Draft Date Sep. 2003 Oct. 2003 Jul. 2004 Remark
0.4
Aug. 2004
0.5
Apr. 2006
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HY5DU28422ET HY5DU28822ET HY5DU281622ET
DESCRIPTION
The Hynix HY5DU28422ET, HY5DU28822ET and HY5DU281622ET are a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density and high bandwidth. The Hynix 128Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
* * * * * * VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) On chip DLL align DQ and DQS transition with CK transition DM mask write data-in at the both rising and falling edges of the data strobe tRAS Lock-out function supported * * * * * * * * All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock Programmable /CAS latency 2 / 2.5 / 3 supported Programmable burst length 2 / 4 / 8 with both sequential and interleave mode Internal four bank operations with single pulsed /RAS Auto refresh and self refresh supported 4096 refresh cycles / 64ms JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Full and Half strength driver option controlled by EMRS
* * *
ORDERING INFORMATION
Part No. HY5DU28422ET-X* HY5DU28822ET-X* HY5DU281622ET-X* Configuration 32Mx4 16Mx8 8Mx16 PACKAGE 400mil 66pin TSOP-II
OPERATING FREQUENCY
Grade CL2 CL2.5 CL3 Remark (CL-tRCD-tRP)
-J -M -K -H -L
133MHz 133MHz 133MHz 100MHz 100MHz
166MHz 133MHz 133MHz 133MHz 125MHz
166MHz -
DDR333 (2.5-3-3) / 166MHz (3-3-3) DDR266 (2-2-2) DDR266A (2-3-3) DDR266B (2.5-3-3) DDR200 (2-2-2) 3
* X means speed grade
Rev. 0.5 / Apr. 2006
HY5DU28422ET HY5DU28822ET HY5DU281622ET PIN CONFIGURATION(TSOP)
x4
VDD NC VDDQ NC DQ0 VSSQ NC NC VDDQ NC DQ1 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
x8
VDD DQ0 VDDQ NC DQ1 VSSQ NC DQ2 VDDQ NC DQ3 VSSQ NC NC VDDQ NC NC VDD NC NC /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
x16
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
x16
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
x8
VSS DQ7 VSSQ NC DQ6 VDDQ NC DQ5 VSSQ NC DQ4 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
x4
VSS NC VSSQ NC DQ3 VDDQ NC NC VSSQ NC DQ2 VDDQ NC NC VSSQ DQS NC VREF VSS DM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
400mil X 875mil 66pin TSOP -II 0.65mm pin pitch
ROW AND COLUMN ADDRESS TABLE
ITEMS Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh 32Mx4 8M x 4 x 4banks A0 - A11 A0-A9, A11 BA0, BA1 A10 4K 16Mx8 4M x 8 x 4banks A0 - A11 A0-A9 BA0, BA1 A10 4K 8Mx16 2M x 16 x 4banks A0 - A11 A0-A8 BA0, BA1 A10 4K
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PIN DESCRIPTION
PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Chip Select: Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. For the x16, LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. For the x16, LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin: Data bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /WE
Input
DM (LDM, UDM)
Input
DQS (LDQS, UDQS) DQ VDD/VSS VDDQ/VSSQ VREF NC
I/O I/O Supply Supply Supply NC
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FUNCTIONAL BLOCK DIAGRAM (32Mx4)
4Banks x 8Mbit x 4 I/O Double Data Rate Synchronous DRAM
Write Data Register 2-bit Prefetch Unit 8 CLK /CLK CKE /CS /RAS /CAS /WE DM Bank Control Command Decoder 8Mx4/Bank0 Sense AMP 8Mx4/Bank1 8Mx4/Bank2 8Mx4/Bank3 Mode Register Row Decoder 8
4
Input Buffer Output Buffer 4
DS
2-bit Prefetch Unit
DQ [0:3]
Column Decoder
ADD BA0, BA1
DQS Address Buffer Column Address Counter CLK_DLL DS CLK /CLK DLL Block Data Strobe Transmitter Data Strobe Receiver
Mode Register
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FUNCTIONAL BLOCK DIAGRAM (16Mx8)
4Banks x 4Mbit x 8 I/O Double Data Rate Synchronous DRAM
Write Data Register 2-bit Prefetch Unit 16 CLK /CLK CKE /CS /RAS /CAS /WE DM Bank Control Command Decoder 4Mx8/Bank0 Sense AMP 4Mx8/Bank1 4Mx8/Bank2 4Mx8/Bank3 Mode Register Row Decoder 16
8
Input Buffer Output Buffer 8
DS
2-bit Prefetch Unit
DQ [0:7]
Column Decoder
ADD BA0,BA1
DQS Address Buffer Column Address Counter CLK_DLL DS CLK /CLK DLL Block Data Strobe Transmitter Data Strobe Receiver
Mode Register
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FUNCTIONAL BLOCK DIAGRAM (8Mx16)
4Banks x 2Mbit x 16 I/O Double Data Rate Synchronous DRAM
Write Data Register 2-bit Prefetch Unit 32 CLK /CLK CKE /CS /RAS /CAS /WE LDM UDM Bank Control Command Decoder 2Mx16/Bank0 Sense AMP 2Mx16/Bank1 2Mx16/Bank2 2Mx16/Bank3 Mode Register Row Decoder 32
16
Input Buffer Output Buffer 16
DS
2-bit Prefetch Unit
DQ[0:15]
Column Decoder
ADD BA0, BA1 Address Buffer Column Address Counter CLK_DLL LDQS UDQS CLK /CLK DLL Block Data Strobe Transmitter Data Strobe Receiver
LDQS, UDQS
Mode Register
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SIMPLIFIED COMMAND TRUTH TABLE
Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X ADDR A10/ AP OP code OP code X V V BA Note 1,2 1,2 1 1 1 1,3 1 1,4 1,5 1 1 1 1 X 1 1 X 1 1 1 1 X 1 1
H
X
L
H
L
L
CA
V X V
H H H H L
X X H L H
L L L L H L H L H L H L
L H L L X H X H X H X V X
H H L L X H X H X H X V
L L H H X H X H X H X V
X
Entry Precharge Power Down Mode Exit
H
L
L
H
Active Power Down Mode
Entry Exit
H L
L H
( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note: 1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Precharge command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Precharge delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
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WRITE MASK TRUTH TABLE
Function Data Write Data-In Mask CKEn-1 H H CKEn X X /CS, /RAS, /CAS, /WE X X DM L H ADDR A10/AP X X BA Note 1 1
Note: 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. In case of x16 data I/O, LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
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OPERATION COMMAND TRUTH TABLE-I
Current State /CS H L L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L WRITE L L L Rev. 0.5 /Apr. 2006 /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP Action NOP or power down3 NOP or power down3 ILLEGAL4 ILLEGAL4 ILLEGAL4 Row Activation NOP Auto Refresh or Self Refresh5 Mode Register Set NOP NOP ILLEGAL4 Begin read: optional AP6 Begin write: optional AP6 ILLEGAL4 Precharge7 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end Terminate burst Term burst, new read:optional AP8 ILLEGAL ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL4 Term burst, new read:optional AP8 Term burst, new write:optional AP 11
HY5DU28422ET HY5DU28822ET HY5DU281622ET
OPERATION COMMAND TRUTH TABLE-II
Current State /CS L WRITE L L L H L L READ WITH AUTOPRECHARGE L L L L L L H L L WRITE AUTOPRECHARGE L L L L L L H L L L PRECHARGE L L L L L /RAS L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /CAS H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L /WE H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP-Enter IDLE after tRP NOP-Enter IDLE after tRP ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,10 NOP-Enter IDLE after tRP ILLEGAL11 ILLEGAL11
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OPERATION COMMAND TRUTH TABLE-III
Current State /CS H L L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L H L L WRITE RECOVERING WITH AUTOPRECHARGE L L L L L L H L REFRESHING L L /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,9,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP - Enter ROW ACT after tWR NOP - Enter ROW ACT after tWR ILLEGAL4 ILLEGAL ILLEGAL ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter precharge after tDPL NOP - Enter precharge after tDPL ILLEGAL4 ILLEGAL4,8,10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tRC NOP - Enter IDLE after tRC ILLEGAL11 ILLEGAL11
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OPERATION COMMAND TRUTH TABLE-IV
Current State /CS L L WRITE L L L H L L L MODE REGISTER ACCESSING L L L L L /RAS H L L L L X H H H H L L L L /CAS L H H L L X H H L L H H L L /WE L H L H L X H L H L H L H L Address BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tMRD NOP - Enter IDLE after tMRD ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11
Note: 1. H - Logic High Level, L - Logic Low Level, X - Don't Care, V - Valid Data Input, BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation. 2. All entries assume that CKE was active(high level) during the preceding clock cycle. 3. If both banks are idle and CKE is inactive(low level), then in power down mode. 4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank. 5. If both banks are idle and CKE is inactive(low level), then self refresh mode. 6. Illegal if tRCD is not met. 7. Illegal if tRAS is not met. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Illegal if tRRD is not met. 10. Illegal for single bank, but legal for other banks in multi-bank devices. 11. Illegal for all banks.
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HY5DU28422ET HY5DU28822ET HY5DU281622ET CKE FUNCTION TRUTH TABLE
Current State CKEn1 H L SELF REFRESH1 L L L L L H L POWER DOWN2 L L L L L H H H ALL BANKS IDLE4 H H H H H L ANY STATE OTHER THAN ABOVE H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X L H L L L L L X X X X X /RAS X X H H H L X X X H H H L X X L X H H H L L X X X X X /CAS X X H H L X X X X H H L X X X L X H H L H L X X X X X /WE X X H L X X X X X H L X X X X H X H L X X L X X X X X /ADD X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit self refresh, enter idle after tSREX Exit self refresh, enter idle after tSREX ILLEGAL ILLEGAL ILLEGAL NOP, continue self refresh INVALID Exit power down, enter idle Exit power down, enter idle ILLEGAL ILLEGAL ILLEGAL NOP, continue power down mode See operation command truth table Enter self refresh Exit power down Exit power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP See operation command truth table ILLEGAL5 INVALID INVALID
Note: When CKE=L, all DQ and DQS must be in Hi-Z state. 1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. All command can be stored after 2 clocks from low to high transition of CKE. 3. Illegal if CLK is suspended or stopped during the power down mode. 4. Self refresh can be entered only from the all banks idle state. 5. Disabling CLK may cause malfunction of any bank which is in active state.
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SIMPLIFIED STATE DIAGRAM
Pow er A p p lie d Pow er On
P re c h a rg e PREALL REFS REFSX MRS EM RS MRS
S e lf R e fre s h
Id le
REFA
A u to R e fre s h
CKEL CKEH
A c t iv e Power Down
ACT
P re c h a rg e Pow er Down
CKEH CKEL B u rs t S to p Read Read W r ite A W r it e Read A Read Read
Row A c t iv e W r it e W r it e
W r it e A Read A W r it e A PRE PRE PRE
Read A
Read A
PRE
P re c h a rg e PR EALL A u t o m a t ic S e q u e n c e Com m and Sequence
P R E A L L = P r e c h a r g e A ll B a n k s M R S = M o d e R e g is t e r S e t E M R S = E x t e n d e d M o d e R e g is t e r Set R E F S = E n t e r S e lf R e f r e s h R E F S X = E x it S e lf R e f r e s h R E F A = A u to R e f r e s h
C K E L = E n te r P o w e r D o w n C K E H = E x it P o w e r D o w n A C T = A c tiv e W r ite A = W r it e w it h A u t o p r e c h a r g e R e a d A = R e a d w ith A u t o p r e c h a r g e P R E = P re c h a rg e
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD, then to VDDQ, and finally to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied anytime after VDDQ, but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. 1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.) * VDD and VDDQ are driven from a single power converter output. * VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation. * VREF tracks VDDQ/2. * A minimum resistance of 42 Ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the VTT supply into any pin. * If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up. Voltage description VDDQ VTT VREF 2. 3. 4. 5. 6. Sequencing After or with VDD After or with VDDQ After or with VDDQ Voltage relationship to avoid latch-up < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V
Start clock and maintain stable clock for a minimum of 200usec. After stable power and clock, apply NOP condition and take CKE high. Issue Extended Mode Register Set (EMRS) to enable DLL. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) Issue Precharge commands for all banks of the device.
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7. 8. Issue 2 or more Auto Refresh commands. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT VREF
/CLK CLK
tIS tIH
CKE
LVCMOS Low Level
CMD
NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
ACT
RD
DM
ADDR
CODE
CODE
CODE
CODE
CODE
A10
CODE
CODE
CODE
CODE
CODE
BA0, BA1
CODE
CODE
CODE
CODE
CODE
DQS
DQ'S
T=200usec tRP tMRD tMRD tRP tRFC tXSRD* Power UP VDD and CK stable Precharge All EMRS Set MRS Set Reset DLL (with A8=H) Precharge All 2 or more Auto Refresh MRS Set (with A8=L) Non-Read Command READ tMRD
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
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MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is programed via MRS command. This command is issued by the low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until reset by another MRS command.
BA1 0
BA0 0
A12
A11
A10
A9
A8
A7
A6
A5 CAS Latency
A4
A3 BT
A2
A1 Burst Length
A0
Operating Mode
BA0 0 1
MRS Type MRS EMRS
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 3 Reserved 1.5 2.5 Reserved A2 A1
A3 0 1
Burst Type Sequential Interleave
Burst Length A0 Sequential 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved
A12~A9 0 0 0 -
A8 0 1 0 -
A7 0 0 1 -
A6~A0 Valid Valid VS
Operating Mode Normal Operation Normal Operation/ Reset DLL
0 1 1 1 1
Vendor specific Test Mode All other states reserved
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BURST DEFINITION
Burst Length 2 Starting Address (A2,A1,A0) XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0 Interleave
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A 2 -Ai when the burst length is set to four and by A 3 -Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table
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The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 2 / 2.5 / 3 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver and the half strength driver are included in this document.
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EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended Mode Register is programmed via the Mode Register Set command (BA0=1 and BA1=0) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation.
BA1 0
BA0 1
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2 0*
A1 DS
A0 DLL
Operating Mode
BA0 0 1
MRS Type MRS EMRS
A0 0 1
DLL enable Enable Disable
A1 0 1
Output Driver Impedance Control Full Strength Driver Half Strength Driver
An~A3 0 _
A2~A0 Valid _
Operating Mode Normal Operation All other states reserved
* This part do not support/QFC function, A2 must be programmed to Zero.
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ABSOLUTE MAXIMUM RATINGS
Parameter
Operating Temperature (Ambient) Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time
Symbol
TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 1 260 10
o
Unit
o
C
oC
V V V mA W C sec
Note: Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter
Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input Leakage Current Output Leakage Current Normal Strength Output Driver
(VOUT=VTT 0.84)
Symbol
VDD VDDQ VIH VIL VTT VREF VIN(DC) VID(DC) VI(RATIO) ILI ILO IOH IOL IOH IOL
Min
2.3 2.3 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ -0.3 0.36 0.71 -2 -5 -16.8 16.8 -13.6 13.6
Typ.
2.5 2.5 VREF 0.5*VDDQ -
Max
2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ VDDQ+0.3 VDDQ+0.6 1.4 2 5 -
Unit
V V V V V V V V uA uA mA mA mA mA
Note
1 2 3 4 5 6 7
Output High Current
(min VDDQ, min VREF, min VTT)
Output Low Current
(min VDDQ, max VREF, max VTT)
Half Strength Output Driver
(VOUT=VTT 0.68)
Output High Current
(min VDDQ, min VREF, min VTT)
Output Low Current
(min VDDQ, max VREF, max VTT)
Note: 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with < 5ns of duration. 3. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed +/- 2% of the dc value. 4. VID is the magnitude of the difference between the input level on CK and the input level on /CK. 5. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1/7 for device drain to source voltages from 0.1 to 1.0. 6. VIN=0 to VDD, All other pins are not tested under VIN =0V. 7. DQs are disabled, VOUT=0 to VDDQ. Rev. 0.5 /Apr. 2006 23
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IDD SPECIFICATION AND CONDITIONS
32Mx4 / 16Mx8 / 8Mx16
Parameter Symbol Test Condition
(TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Speed -J -M -K -H -L
Unit Note
Operating Current
IDD0
One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle One bank; Active - Read - Precharge; Burst=2; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE=High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM One bank active; Power down mode; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min) - 8*tCK for DDR200 at 100Mhz, 10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh CKE=<0.2V; External clock on; tCK=tCK(min) Four bank interleaving with BL=4, Refer to the following page for detailed test condition
110
100
90
mA
Operating Current
IDD1
110
100
90
mA
Precharge Power Down Standby Current
IDD2P
20
15
15
mA
Idle Standby Current
IDD2F
50
45
40
mA
Active Power Down Standby Current
IDD3P
20
20
20
mA
Active Standby Current
IDD3N
60
50
40
mA
Operating Current
IDD4R
160
150
140
mA
Operating Current
IDD4W
160
150
140
mA
Auto Refresh Current
IDD5
180
170
160
mA
Self Refresh Current Operating Current Four Bank Operation
IDD6 IDD7
2 250
2 230
2 200
mA mA
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DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7
IDD1: Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. lout = 0mA 2. Timing patterns - DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=2, tRCD = 2*tCK, tRAS = 5*tCK Read: A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing - DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 6*tCK Read: A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR266(133Mhz, CL=2): tCK = 7.5ns, CL=2, BL=2, tRCD = 2*tCK, tRC = 8*tCK, tRAS = 6*tCK Read: A0 N R0 N N N P0 N A0 N - repeat the same timing with random address changing 50% of data changing at every burst - DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2, BL=2, tRCD = 3*tCK, tRC = 10*tCK, tRAS = 7*tCK Read: A0 N N R0 N N N P0 N N A0 N - repeat the same timing with random address changing 50% of data changing at every burst Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP
IDD7: Operating current: Four bank operation
1. Four banks are being interleaved with tRC(min), Burst Mode, Address and Control inputs on NOP edge are not changing. lout = 0mA 2. Timing patterns - DDR200(100Mhz, CL=2): tCK = 10ns, CL2, BL=4, tRRD = 2*tCK, tRCD= 3*tCK, Read with Autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - DDR266B(133Mhz, CL=2.5): tCK = 7.5ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - DDR266A (133Mhz, CL=2): tCK = 7.5ns, CL2=2, BL=4, tRRD = 2*tCK, tRCD = 3*tCK Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst - DDR333(166Mhz, CL=2.5): tCK = 6ns, CL=2.5, BL=4, tRRD = 2*tCK, tRCD = 3*tCK, Read with autoprecharge Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing 50% of data changing at every burst Legend: A=Activate, R=Read, W=Write, P=Precharge, N=NOP
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AC OPERATING CONDITIONS (TA=0 to 70 oC, Voltage referenced to VSS = 0V)
Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ + 0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note
Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.31 VREF - 0.31 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns pF
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AC Overshoot/Undershoot Specification for Address and Control Pins
This specification is intended for devices with no clamp protection and is guaranteed by design
Parameter Maximum peak amplitude allowed for overshoot (See Figure 1): Maximum peak amplitude allowed for undershoot (See Figure 1): The area between the overshoot signal and VDD must be less than or equal to (See Figure 1): The area between the undershoot signal and GND must be less than or equal to (See Figure 1):
5 4 3 Max. amplitude = 1.5V
Specification DDR333 1.5V 1.5V 4.5V - ns 4.5V - ns DDR200/266 1.5V 1.5V 4.5V - ns 4.5V - ns
Overshoot
Volts(V)
2 1 0 -1 -2 -3 0 1 2 3 4 5 6 Max. area = 4.5V-ns
VDD
GND
Undershoot
Time(ns)
Figure 1: Address and Control AC Overshoot and Undershoot Definition
Overshoot/Undershoot Specification for Data, Strobe, and Mask Pins
Parameter Maximum peak amplitude allowed for overshoot (See Figure 2): Maximum peak amplitude allowed for undershoot (See Figure 2): The area between the overshoot signal and VDD must be less than or equal to (See Figure 2): The area between the undershoot signal and GND must be less than or equal to (See Figure 2):
5 4 3 Max. amplitude = 1.2V
Specification DDR333 1.2V 1.2V 2.4V - ns 2.4V - ns DDR200/266 1.2V 1.2V 2.4V - ns 2.4V - ns
Overshoot
Volts(V)
2 1 0 -1 -2 -3 0 1 2 3 4 5 6 Max. area = 2.4V-ns
VDD
GND
Undershoot
Time(ns)
Figure 2: DQ/DM/DQS AC Overshoot and Undershoot Definition
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AC CHARACTERISTICS I (AC operating conditions unless otherwise noted)
Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time CL = 3 System Clock Cycle Time CL = 2.5 CL = 2 Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Valid Data Output Window Data-out high-impedance window from CK, /CK Data-out low-impedance window from CK, /CK Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tDV tHZ tLZ tIS tIH tCK Symbol tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL DDR333 Min 60 72 42 18 18 12 1 18 15 1
(tWR/tCK) + (tRP/tCK) 6

DDR266(2-2-2) Min 60 75 45 15 15 15 1 15 15 1
(tWR/tCK) + (tRP/tCK) -
Max 70K 12 12 12 0.55 0.55 0.7 0.6 0.45 0.55
Max 120K 12 12 0.55 0.55 0.75 0.75 0.5 0.75
Unit
Note
ns ns ns ns ns ns CK ns ns CK CK ns ns ns CK CK ns ns ns ns ns ns ns ns ns ns ns 17 17 2,3,5,6 2,3,5,6 1, 10 1,9 10 15 16
6 7.5 0.45 0.45 -0.7 -0.6 tHP -tQHS min (tCL,tCH) -
7.5 7.5 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) -
tQH-tDQSQ -0.7 -0.7 0.75 0.75 0.7 0.7 -
tQH-tDQSQ -0.75 -0.75 0.9 0.9 0.75 0.75 -
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DDR333 Min 0.8 0.8 2.2 0.35 0.35 0.75 0.45 0.45 1.75 0.9 0.4 0 0.25 0.4 2 200 1.25 1.1 0.6 0.6 15.6 Max DDR266(2-2-2) Min 1.0 1.0 2.2 0.35 0.35 0.72 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 200 1.28 1.1 0.6 0.6 15.6 Max -
Parameter Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval
Symbol tIS tIH tIPW tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI
Unit
Note
ns ns ns CK CK CK ns ns ns CK CK CK CK CK CK CK us
2,4,5,6 2,4,5,6 6
6,7, 11~13 6,7, 11~13
8
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AC CHARACTERISTICS II (AC operating conditions unless otherwise noted)
Parameter Row Cycle Time Auto Refresh Row Cycle Time Row Active Time Active to Read with Auto Precharge Delay Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Write to Read Command Delay Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Valid Data Output Window Data-out high-impedance window from CK, /CK Data-out low-impedance window from CK, /CK CL = 2.5 CL = 2 Symbol tRC tRFC tRAS tRAP tRCD tRRD tCCD tRP tWR tWTR tDAL DDR266A Min 65 75 45 20 20 15 1 20 15 1
(tWR/tCK) + (tRP/tCK)

DDR266B Min 65 75 45 20 20 15 1 20 15 1
(tWR/tCK) + (tRP/tCK)
DDR200 Min 70 80 50 20 20 15 1 20 15 1
(tWR/tCK) + (tRP/tCK)
Max 120K 12 12 0.55 0.55 0.75 0.75 0.5 0.75
Max 120K 12 12 0.55 0.55 0.75 0.75 0.5 0.75
Max 120k 12 12 0.55 0.55 0.8 0.8 0.6 0.75
Unit
Note
ns ns ns ns ns ns CK ns ns CK CK ns ns CK CK ns ns ns ns ns ns ns ns ns 17 17 1, 10 1,9 10 15 16
tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tDV tHZ tLZ
7.5 7.5 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) -
7.5 10 0.45 0.45 -0.75 -0.75 tHP -tQHS min (tCL,tCH) -
8.0 10 0.45 0.45 -0.8 -0.8 tHP -tQHS min (tCL,tCH) -
tQH-tDQSQ -0.75 -0.75 0.75 0.75
tQH-tDQSQ -0.75 -0.75 0.75 0.75
tQH-tDQSQ -0.8 -0.8 0.8 0.8
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-continuedDDR266A Min 0.9 0.9 1.0 1.0 2.2 0.35 0.35 0.75 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 200 1.25 1.1 0.6 0.6 15.6 Max DDR266B Min 0.9 0.9 1.0 1.0 2.2 0.35 0.35 0.75 0.5 0.5 1.75 0.9 0.4 0 0.25 0.4 2 200 1.25 1.1 0.6 0.6 15.6 Max DDR200 Min 1.1 1.1 1.1 1.1 2.5 0.35 0.35 0.75 0.6 0.6 2 0.9 0.4 0 0.25 0.4 2 200 Max 1.25 1.1 0.6 0.6 15.6
Parameter Input Setup Time (fast slew rate) Input Hold Time (fast slew rate) Input Setup Time (slow slew rate) Input Hold Time (slow slew rate) Input Pulse Width Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-in Hold Time to DQS-In (DQ & DM) DQ & DM Input Pulse Width Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Average Periodic Refresh Interval
Symbol tIS tIH tIS tIH tIPW tDQSH tDQSL tDQSS tDS tDH tDIPW tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tREFI
Unit
Note
ns ns ns ns ns CK CK CK ns ns ns CK CK CK CK CK CK CK us
2,3,5,6 2,3,5,6 2,4,5,6 2,4,5,6 6
6,7, 11~13
8
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Note: 1. 2. 3. 4. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock: A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. For command/address input slew rate>=1.0V/ns For command/address input slew rate>=0.5V/ns and <1.0V/ns This Derating Table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 5. 6. 7. 8. 9. CK, /CK slew rates are>=1.0V/ns These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by design or tester correlation. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS): DQ, LDM/UDM. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). Delta tIS ps 0 +50 +100 Delta tIH ps 0 0 0
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects and p-channel to n-channel variation of the output drivers. 11. This derating table is used to increase tDS/tDH in case where the input slew-rate is below 0.5V/ns. Input Setup / Hold Slew-rate Derating Table. Input Setup / Hold Slew-rate V/ns 0.5 0.4 0.3 Delta tDS ps 0 +75 +150 Delta tDH ps 0 +75 +150
12. I/O Setup/Hold Plateau Derating. This derating table is used to increase tDS/tDH in case where the input level is flat below VREF +/-310mV for a duration of up to 2ns. I/O Input Level mV +280 Delta tDS ps +50 Delta tDH ps +50
13. I/O Setup/Hold Delta Inverse Slew Rate Derating. This derating table is used to increase tDS/tDH in case where the DQ and DQS slew rates differ. The Delta Inverse Slew Rate is calculated as (1/SlewRate1)-(1/SlewRate2). For example, if slew rate 1= 0.5V/ns and Slew Rate2=0.4V/n then the Delta Inverse Slew Rate=-0.5ns/V. (1/SlewRate1)-(1/SlewRate2) ns/V 0 +/-0.25 +/- 0.5 Delta tDS ps 0 +50 +100 Delta tDH ps 0 +50 +100
Rev. 0.5 /Apr. 2006
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14. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic. 15. tDAL = (tDPL / tCK) + (tRP / tCK). For each of the terms above, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. Example: For DDR266B at CL=2.5 and tCK = 7.5 ns, tDAL = (15 ns / 7.5 ns) + (20 ns / 7.5 ns) = (2.00) + (2.67) Round up each non-integer to the next highest integer: = (2) + (3), tDAL = 5 clocks 16. For the parts which do not has internal RAS lockout circuit, Active to Read with Auto precharge delay should be tRAS - (BL/2) x tCK. 17. tHZ and tLZ transitions occur in the same access time windows as valid data trasitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ).
Rev. 0.5 /Apr. 2006
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CAPACITANCE (TA=25oC, f=100MHz)
Parameter Input Clock Capacitance Delta Input Clock Capacitance Input Capacitance Delta Input Capacitance Input / Output Capacitance Delta Input / Output Capacitance CK, /CK CK, /CK All other input-only pins All other input-only pins DQ, DQS, DM DQ, DQS, DM Pin Symbol CI1 Delta CI1 CI1 Delta CI2 CIO Delta CIO Min 2.0 2.0 4.0 Max 3.0 0.25 3.0 0.5 5.0 0.5 Unit pF pF pF pF pF pF
Note: 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
RT=50
Output Zo=50 VREF
CL=30pF
Rev. 0.5 /Apr. 2006
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PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396) BASE PLANE
22.33 (0.879) 22.12 (0.871)
0 ~ 5 Deg.
0.65 (0.0256) BSC
0.35 (0.0138) 0.25 (0.0098)
SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047)
1.194 (0.0470) 0.991 (0.0390)
Note: Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm.
Rev. 0.5 /Apr. 2006
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